1. Field of the Invention
This invention relates to a keying input apparatus for any type of electronic processor and, more particularly, to such a keying input apparatus suited for a desk top type electronic calculator, an electronic cash registor, and the like including a display device.
2. Description of the Prior Art
A key board provided with a plurality of key switches is used for the desk top type electronic calcurator. Such information processing apparatus as the desk top type electronic calculator typically comprises a circuit body for storing and processing the numerical information, switching means for inputting signals for processing the numerical information, and a display device for displaying the numerical information. The conventional key board is constructed so that a given voltage is applied commonly to one end of each key switch, and each key switch is connected, at its other end, to a circuit having storage, caluculation and control functions. Terminals or pins the number of which is the same as the number of the key switches are required for the circuit. Accordingly, the number of wiring corresponding to the number of the key switches is also required. The circuit body of a typical desk top type electronic calculator uses an integrated circuit. However, in using such an integrated circuit, the cost of the desk top type electronic calculator becomes higher extremely with the increased number of the terminals or the pins, and thus with the increased number of the wirings. Therefore, it is required to minimize them.
In order to meet such requirement, it has been proposed that a timing signal is employed as a key input signal, such that the timing signal for operation of the apparatus is inputted to the circuit body through one line and thus one terminal by the key input means, the timing signal being coded using matrix means in the circuit body. However, in this type of system, the circuit construction of the matrix means itself becomes complex, and many output lines are required in deriving the output signal from the matrix means. Accordingly, according to such a system, a scale of integration of integrated circuits is lowered, which will be an obstacle to reduction of the costs.
An information input apparatus has been proposed heretofore wherein the number of the pins or terminals to be provided already in the circuit body is reduced, the circuit structure is simplified to improve the scale of integration of the integrated circuit, and thereby the cost is reduced. The information input apparatus as heretofore proposed uses, as an input signal, a timing signal which is composed of digit timing pulses each including a plurality of bit timing pulses, which are used for the numerical display and the numerical information processing of the desk top type electronic calculator. Such timing signals are generated from a timing signal generating circuit provided in the circuit body of the desk top type electronic calculator. A plurality of key switches are provided, on the key board, remotely from the circuit body and a plurality of digit timing pulses of different timing are individually applied to one end of a plurality of key switches. In the wiring thereof, the existing digit timing signal output terminals are used which are provided indispensably in the circuit body to apply the timing signals to the display device for display driving operation of the display device. The other end of each key switch is commonly connected to the circuit body by a single wiring. In other words, time-shared input signals are inputted to the circuit body by a single line. Accordingly, the number of the wires and, connection terminals is reduced remarkably as compared with that of conventional such apparatus. A coded signal generating means is provided which converts into coded signals the timing signals which are composed of bit timing pulses including a plurality of bit timing pulses. More specifically, the coded signal generating means uses the bit timing signal to generate a binary coded signal and a desired coded signal is extracted by the timing signal from the depressed key switch during the subsequent digit timing pulse period. Thus, the digit timing pulses to be inputted by the key switch are converted into coded signals for use in calculation, etc.
Thus, according to the apparatus described in the referenced patent application, the bit timing pulses included in the digit timing signal are used to synchronously generate the coded signal corresponding to the digit timing pulse. Accordingly, the circuit construction is comparatively simplified. Also, the number of the output signal lines at which the coded signal is derived may be unity, whereby the degree to which the circuits may be integrated is increased substantially as compared with systems employing matrix means. Accordingly, a large cost decrease is possible.
However, the apparatus described in the referenced patent application has the following disadvantages. Namely, in a case where the number of key switches is less than that of the digit timing pulses of the timing signal, no problem arises, while in a reverse case, the key switches have to be divided into a plurality of groups. Therefore, two or more common input signal lines and common connection terminals from the key switches are required. Since the number of digit timing pulses of the timing signal is normally selected to be a value related to the digit number of the display device, the number of digit timing pulses can not be more than necessary. Accordingly, if number of the key switches can be increased without increasing number of the digit timing pulses, and the number of terminals provided in the circuit body, it is highly desirable in reducing the cost of the information processing apparatus such as a desk top electronic calculator. The other disadvantage with the invention disclosed in the refrenced patent application is that information identification errors are liable to be caused when the information input signals to be inputted successively are in rapid succession in terms of digit timing, since the information signal inputs are sent in series by a single line.